The present invention relates, in general, to electronics and, more particularly, to semiconductor die packages and methods for packaging semiconductor die.
In the past, the semiconductor industry used a variety of package configurations to increase the packing density of semiconductor die in a system. The increased demand for electronic devices increased the demand for smaller, lighter, and yet more functional semiconductor devices and resulted in a demand for semiconductor packages that had increased semiconductor packaging densities with smaller outlines and mounting footprints. In some embodiments, semiconductor die were vertically stacked on top of one another with an interposing layer of adhesive attached to the semiconductor die in order to couple the semiconductor die together. The die were attached to a glass-epoxy type printed circuit board substrate or other similar substrate. The semiconductor die were then wire bonded to the substrate to form electrical interconnections between the substrate and the semiconductor die. One example of such a package configuration is disclosed in U.S. Pat. No. 6,650,019 issued to Thomas B. Glenn et al. on Nov. 18, 2003. Another example of an electronic assembly with stacked integrated circuit die is disclosed in U.S. Pat. No. 7,030,317, issued to Todd P. Oman on Apr. 18, 2006.
Accordingly, it would be advantageous to have a semiconductor component and method of stacking semiconductor die to manufacture the semiconductor component without increasing the footprint of the semiconductor component. It would be of further advantage for the semiconductor component and method to be cost and time efficient to implement.